Research Prototypes



The first demonstration of truly voltage-scalable quasi-resonant clocking
Fahim U. Rahman, Visvesh S. Sathe [ISSCC’16]

Prototype demonstrating an optimized ECoG signal chain with reduced noise and ADC requirements, resolved from specific characteristics of ECoG signals.
William A. Smith [ESSCIRC’14 [TBIOCAS’16]

RF2: The first-ever fully integrated resonant clocked datapath. The design, operating at 1GHz in 0.13um CMOS, was implemented in a fully ASIC design flow and featured distributed clock generation to automate the resonant clock generation.
Visvesh Sathe,  Jerry Kao [VLSI Symp, JSSC]

rf1_dieshot

RF1: Single phase resonant clocked ASIC with programmable operating frequency of 0.8GHz-1.2GHz
Visvesh Sathe, Jerry Kao [CICC, JSSC]

Boost Logic: The first-ever GHz-class charge-recovery logic. Operating at 1.1GHz, the fully integrated logic implemented a novel charge recovery logic, “Boost-Logic”, to achieve dramatic speed improvement over the state-of-the-art – Previous charge-recovery logic operating frequencies were in the 200MHz range
Visvesh Sathe  [ISSCC, JSSC]