Patents

  1. V. S. Sathe, S. Naffziger, and S. Arekapudi, “Sense amplifier monotizer”, US Patent 8710868, Apr. 29, 2014.
  2. V. S. Sathe and S. Naffziger, “Transitioning between resonant clocking mode and conventional clocking mode” US Patent 20140062566, Mar.6, 2014
  3. V. S. Sathe, S. Naffziger, “Controlling impedance of a switch using high impedance voltage sources to provide more efficient clocking”, US Patent 20140062563, Mar. 6, 2014.
  4. V. S. Sathe and S. Naffziger “Programmable clock driver”, US Patent 20140062564, Mar. 6, 2014.
  5. V. S. Sathe, S. Naffziger and S. Arekapudi “Clock driver for frequency-scalable systems”, US Patent 20140062565, Mar.6, 2014.
  6. V. S. Sathe and S. Naffziger, “Oscillator device and method thereof,” US Patent 8373512, Feb. 12, 2013.
  7. V. S. Sathe, S. Naffziger and S. Pant, “Clock stretcher for voltage droop mitigation,” US Patent 20120187991, Jul. 26, 2012.
  8. S. Kosonocky, S. Naffziger, and V. S. Sathe “Interposer including voltage regulator and method thereof,” US Patent 8193799 Jun. 5, 2012.
  9. J-Y. Chueh, J. Kao, V. S. Sathe, and M. C. Papaefthymiou, “Clock distribution network architecture with clock skew management,” US Patent 7956664, 3 Dec. 2007.
  10. J-Y. Chueh, J. Kao, V. S. Sathe, and M. C. Papaefthymiou, “Clock distribution network architecture for resonant-clocked systems,” US Patent 7719316, 3 Dec. 2007.
  11. J-Y Chueh, J. Kao, V. S. Sathe, and M. C. Papaefthymiou, “Clock distribution network architecture with resonant clock gating,” US Patent 7719317, 3 Dec. 2007 .
  12. M. C. Papaefthymiou, V. S. Sathe, and C. H. Ziesler, “Energy recovery boost logic,” US Patent 7355454, 15 Jun 2005.