Journal Articles

  1. William A. Smith, Brian J. Mogen, Eberhard E. Fetz, Visvesh S. Sathe, Brian P. Otis, “Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 μW Analog Front End with Reduced ADC Resolution Requirements”, to appear in IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), 2016
  2. V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. C. Papaefthymiou, S. Naffziger, “Resonant Clock Design for a Power-efficient, High-volume x86-64 Microprocessor”, to appear in IEEE Journal of Solid-State Circuits, Invited paper, Special Issue on ISSCC ‘12, Jan. 2013.[pdf]
  3. W. S. Ma, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou, “187MHz subthreshold-supply charge-recovery FIR,” IEEE Journal of Solid-State Circuits, Invited paper, Special Issue on 2009 Symposium on VLSI Circuits, vol. 45, no. 4, pp. 793–803, Apr. 2010.[pdf]
  4. V. S. Sathe, J. Kao and M. C. Papaefthymiou, “Resonant-clock latch-based design”, IEEE Journal of Solid-State Circuits, Invited paper, Special Issue on 2007 Symposium on VLSI Circuits, vol. 43, no. 4, pp. 864–873, Apr. 2008.[pdf]
  5. V. S. Sathe, J.-Y. Chueh, and M. C. Papaefthymiou, “Energy-efficient GHz-class charge-recovery logic,” IEEE Journal of Solid-State Circuits, Invited paper, Special Issue on ISSCC ‘06, vol. 42, no. 1, pp. 38–47, Jan. 2007.[pdf]
  6. V. S. Sathe, M. C. Papaefthymiou, S. V. Kosonocky, and S. Kim, “On-chip synchronous communication between clock domains with quotient frequencies,” Electronics Letters, vol. 43, no. 9, pp. 497–499, Apr. 2007.[pdf]