Conference Publications

  1. “A 40nm CMOS Single-Ended Switch-Capacitor Harmonic-Rejection Power Amplifier for ZigBee Applications”, to appear in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2016
  2. Fahim U. Rahman, Visvesh S. Sathe, “Voltage-Scalable Frequency-Independent
    Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System”, IEEE International Solid-State Circuits Conference (ISSCC), 2016 [link]
  3. Mi, D.Mandal; V. S. Sathe; B.Bakkologlu, J.Seo, “Fully-Integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015 [pdf]
  4. V. S. Sathe, J.Seo,“Analysis and optimization of CMOS switched- capacitor converter”, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2015 [pdf]
  5. V. S. Sathe, “Quasi-Resonant Clocking : A Run-time Control Approach for True Voltage-Frequency-Scalability,” IEEE /ACM International Symposium on Low Power Electronics and Design (ISLPED), 2014  [pdf]
  6. K. Sankaragomathi, W. A. Smith and V. S Sathe, “A deterministic-dither-based, all-digital system for on-chip power supply noise measurement”, IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2014 [pdf]
  7. V. S. Sathe, A. Loke, T. Khan, V. Ross, A. Raman, G. Vandevalk, P. Papadopoulos and N. Provatas, “Inductor Design for Global Resonant Clock Distribution,” Design Automatic Conference (DAC), 2013
  8. V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. Papaefthymiou and S. Naffziger, “Resonant clock design for a power-efficient, high-volume x86-64 microprocessor,” in IEEE Int. Solid-State Circuits Conference (ISSCC), pp. 68-69 San Francisco, CA, Feb. 2012. An extended version of this paper was invited for publication in the IEEE Journal of Solid-State Circuits, Special issue on ISSCC ’12. [pdf]
  9. H.-P. Le, M. Seeman, S. Sanders, V. S. Sathe, S. Naffziger, and E. Alon, “A 32nm fully-integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency,” in IEEE Int. Solid-State Circuits Conference (ISSCC), pp. 210–211, San Francisco, CA, Feb. 2010.[pdf]
  10. J. C. Kao, W. S. Ma, V. S. Sathe, and M. C. Papaefthymiou, “A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead,” in IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 160–163, Athens, Greece, Sep. 2009.[pdf]
  11. M. C. Papaefthymiou, A. Ishii, J. Kao., and V. S. Sathe, “A resonant-clock 200MHz ARM926EJ-S™ microcontroller,” in IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 356–359, Athens, Greece, Sep. 2009.[pdf]
  12. W. S. Ma, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou, “A 187MHz subthreshold-supply robust FIR filter with charge-recovery logic,” in IEEE Symposium VLSI Circuits, pp. 202–203, Kyoto, Japan, Jun. 2009. Invited for publication in IEEE Journal of Solid-State Circuits (JSSC), Special Issue on VLSI Circuits ’09.[pdf]
  13. V. S. Sathe, J. C. Kao, and M. C. Papaefthymiou, “RF2: A 1GHz FIR filter with distributed resonant clock generator,” in IEEE Symposium VLSI Circuits, pp. 44–45, Kyoto, Japan, Jun. 2007. Invited for publication in IEEE Journal of Solid-State Circuits (JSSC), Special Issue on VLSI Circuits ’07.[pdf]
  14. V. S. Sathe, J-Y. Chueh, and M. C. Papaefthymiou, “A 1.1GHz charge-recovery logic,” in IEEE Int. Solid-State Circuits Conference (ISSCC), pp. 1540–1549, San Francisco, CA, Feb. 2006. Invited for publication in IEEE Journal of Solid-State Circuits (JSSC), Special Issue on ISSCC’06. [pdf]
  15. 11. V. S. Sathe, J. C. Kao, and M. C. Papaefthymiou, “A 0.8-1.2GHz single-phase resonant-clocked FIR filter with level-sensitive latches,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 583–586, San Jose, CA, Sep. 2007.[pdf]
  16. J.-Y. Chueh, V. S. Sathe, and M. C. Papaefthymiou, “900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 777–780, San Jose, CA, Sep. 2006.[pdf]
  17. V. S. Sathe, C. H. Ziesler, and M. C. Papaefthymiou, “A GHz-class charge-recovery logic,” in Int. Symposium Low-Power Electronic Design (ISPLED), pp. 91–94, San Diego, CA, Aug. 2005. [pdf]
  18. V. S. Sathe, J-Y. Chueh, J. Kim, C.H. Ziesler, S. Kim, and M. C. Papaefthymiou, “Fast, efficient, recovering and irreversible,” in Conference on Computing Frontiers, pp. 407–413, Ischia, Italy, May 2005.[pdf]
  19. J-Y. Chueh, V. S. Sathe and M. C. Papaefthymiou, “Two-phase resonant clock distribution,” in Int. Symposium VLSI, pp. 65–70, Tampa, FL, May 2005.[pdf]
  20. V. S. Sathe, C. H. Ziesler and M. C. Papaefthymiou, “Boost logic: a high-speed energy-recovery circuit family,” in Int. Symposium VLSI, pp. 22–27, Tampa, FL, May 2005.[pdf]
  21. V. S. Sathe, S. Kim, S. Kosonocky, and M. C. Papaefthymiou, “A synchronous interface for SoCs with multiple clock domains,” in SOC Conference, pp. 173–174, Newport Beach, CA, Sep. 2004 [pdf]
  22. C. H. Ziesler, J. Kim , V. S. Sathe and M. C. Papaefthymiou, “A 225 MHz resonant clocked ASIC,” in Int. Symposium Low-Power Electronic Design (ISLPED), pp. 48–53, Seoul, South Korea, Aug. 2003 [pdf]